1. Field of the Invention
The present invention relates to semiconductor storage devices such as SRAM (Static Random Access Memory).
2. Description of the Background Art
In recent years, with speeding up of MPU (Micro Processor Unit), attempts are being made to speed up the access time of SRAM which is a kind of semiconductor storage device. Furthermore, with developments of multifunctional systems around the MPU, an increase in its capacity is also in progress.
FIG. 11 is a circuit configuration diagram showing an example of a configuration of a conventional SRAM. As shown in the figure, memory cells 11 and 12 in the same column are formed between a common bit line pair BL and BL. The memory cells 11 and 12 provided in different rows are connected to different word lines WL1 and WL2, respectively. In practice, memory cells are arranged in a matrix, but the memory cells 11 and 12 and the vicinity thereof only are shown in FIG. 11.
All the word lines WL (WL1, WL2, . . . ) are connected to a row decoder 1. The row decoder I captures row address signals RAD from outside through a row address buffer 2 and decodes the row address signals RAD to selectively activate word lines WL.
One pair of ends of the bit line pair BL and BL is connected to a power-supply Vcc through N-channel transistors T1 and T2 of common gate/drain. The transistors T1, T2 and the power-supply Vcc constitute a bit line load circuit. The other ends of the bit line pair BL and BL are connected to an I/O line pair I/O and I/O through transfer gates T3 and T4 of N-channel.
The gates of the transfer gates T3 and T4 are connected to an output line of a column decoder 3. The column decoder 3 captures column address signals CAD from outside through a column address buffer 4 and decodes the column address signals CAD to selectively activate its output lines.
One pair of ends of the I/O line pair I/O and I/O is connected to a power-supply Vcc through N-channel transistors T5 and T6 of common gate/drain. The transistors T5, T6 and the power-supply Vcc constitute an I/O line load circuit. The other ends of the I/O line pair I/O and I/O are connected to a sense amplifier 5.
The sense amplifier 5 detects a potential difference occurring between the I/O line pair I/O and I/O and outputs to an output buffer 6 an amplified signal thereof as a sense amplifier output signal SA. The output buffer 6 further amplifies the sense amplifier output signal SA and outputs an output signal OUT the outside.
An ATD control circuit 7 receives a row address signal RAD and a column address signal CAD, and when detecting a change in address of the row address signal RAD or the column address signal CAD, it raises normally an L level ATD control signal S7 to an H level during a predetermined period.
An N-channel transistor T7 for equalizing is interposed between the bit line pair BL and BL, and the ATD control signal S7 of the ATD control circuit 7 is applied to the gate of the transistor T7.
FIG. 12 is a circuit diagram showing the internal structure of the memory cell 11 (12). As shown in the figure, the memory cell 11 is of the high resistance load type cell structure, which includes four NMOS transistors Q1-Q4 and two resistors R1 and R2. The load resistor R1 and the transistor Q1 for driver are provided in series between a power-supply Vcc and ground, and the load resistor R2 and the transistor Q2 for driver are provided in series also between a power-supply Vcc and ground. A node N1 between the resistor R1 and the transistor Q1 is connected to a gate of the transistor Q2, and a node N2 between the resistor R2 and the transistor Q2 is connected to a gate of the transistor Q1. The transistor Q3 for access is interposed between the node N1 and the bit line BL, and the transistor Q4 for access is interposed between the node N2 and the bit line BL. The gates of these transistors Q3 and Q4 are connected to the word line WL. FIG. 13 is a waveform diagram illustrating read operation according to the ATD system of the SRAM shown in FIGS. 11 and 12.
Referring to FIG. 13, the read operation of data stored in the memory cell 11 will be described below.
First, a row address signal RAD and a column address signal CAD indicating selection of the word line WL and the bit line BL to which the memory cell 11 is connected are applied the row decoder 1 and the column decoder 3 through the row address buffer 2 and the column address buffer 4, respectively.
Then, the row decoder 1 brings only the word line WL 1 in FIG. 11 into an active state (an H level) and the column decoder 3 turns on only the transfer gates T3 and T4 which are connected to the bit line pair BL and BL to which the memory cell 11 is connected to electrically connect the bit line pair BL, BL to which the memory cell 11 is connected and the I/O line pair I/O, I/O.
Now, if the node N1 of the memory cell 11 (refer to FIG. 12) is at the H level and the node N2 is at the L level, the transistor Q1 of the memory cell 11 turns off and the transistor Q2 turns on. At this time since the word line WL1 is at the H level, both of the transistors Q3 and Q4 turn on.
Accordingly, since the transistor T2, the transistor Q4 for access and the transistor Q2 for driver of the memory cell 11 turn on, direct current flows in the bit line BL path including the power-supply Vcc.fwdarw.the transistor T2.fwdarw.the bit line BL.fwdarw.the transistor Q4.fwdarw.the transistor Q2.fwdarw.the ground level. On the other hand, since the transistor Q3 of the memory cell 11 turns off, the direct current does not flow in the bit line BL path including the power-supply Vcc.fwdarw.the transistor T1.fwdarw.the bit line BL.fwdarw.the transistor Q3.fwdarw.the transistor Q1.fwdarw.the ground level.
As a result, if a threshold voltage of the transistors T1 and T2 is represented as VT, the potential of the bit line BL, with no direct current flowing in the bit line BL path, is represented as (Vcc-VT), and the potential of the bit line BL, with direct current flowing in the bit line BL path, is represented as (Vcc-VT-.DELTA.V), which is a decrease of .DELTA.V(&gt;0) from (Vcc-VT) because the power-supply Vcc is resistance-divided due to respective on-resistances of the transistors T2, Q2 and Q4. The .DELTA.V is called bit line amplitude, which is normally about 50 mV-500 mV and adjusted with magnification of bit line load. The bit line amplitude .DELTA.V appears between the I/O line pair, I/O and I/O, through the transfer gates T3 and T4.
The bit line amplitude .DELTA.V appearing between the I/O line pair, I/O and I/O, is detected and amplified by the sense amplifier 5 and outputted as a sense amplifier output signal SA, which is further amplified by the output buffer 6 and outputted as an output signal OUT. Although the equalize potential of the bit line pair BL and BL and the sense center potential of the sense amplifier 5 are shown at different levels in FIG. 13, those are the same potential VC in practice.
During this read operation, when the ATD control circuit 7 detects an address change of the row address signal RAD or the column address signal CAD, as shown in FIG. 13, the ATD control signal S7 is raised to the H level in a predetermined period and the transistor T7 interposed between the bit line pair BL and BL is turned on to equalize the potential of the bit line pair BL and BL.
In FIG. 13, for convenience of description, the rise time of the ATD control signal S7 is shown at timing which is later than the time of determination of the selection word line WL, but those are actually almost at the same timing.
The reason why the ATD control signal S7 is raised to the H level pulse in the predetermined period and the potential on the bit line pair BL and BL are equalized when an address change is detected will be described below.
For example, assuming that the node N1 of the memory cell 11 is at the H level, the node N2 is at the L level, and the node N1 of the memory cell 12 is at the L level and the node 2 is at the H level, the case in which stored data in the memory cell 11 and the memory cell 12 are continuously read out will be described.
First, the read operation of the memory cell 11 is made by selecting the word line WL1 and the bit line BL to which the memory cell 11 is connected as described above. As the result, the potential of the bit line BL is (Vcc-VT) and the potential of the bit line BL is (Vcc-VT-.DELTA.V).
Next, it moves to a read operation of the memory cell 12 and the word line WL2 and the bit line BL to which the memory cell 12 is connected are selected.
At this time, if it were not for the equalizing operation by the ATD control circuit 7 and the transistor T7, it is necessary to decrease the potential of the bit line BL as (Vcc-VT).fwdarw.(Vcc-VT-.DELTA.V) and increase the potential of the bit line BL as (Vcc-VT-.DELTA.V).fwdarw.(Vcc-VT) only by the driving ability of the memory cell 12.
That is, since the potential change of bit line amplitude .DELTA.V must be caused on the bit line pair BL and BL, respectively, with only the memory cell 12 having the small driving ability, it is time-consuming and high speed reading is impossible.
Accordingly, after the potentials of the bit line pair BL and BL are equalized to the center potential VC ((Vcc-Vt-.DELTA.V)&lt;VC&lt;(Vcc-VT)) at a high speed by the equalizing operation of the ATD control circuit 7 and the transistor T7, the potential of the bit line BL is decreased as VC.fwdarw.(Vcc-VT-.DELTA.V) and the potential of the bit line BL is increased as VC.fwdarw.(Vcc-VT) only with the driving ability of the memory cell 12.
That is to say, when inverting the potential levels of the bit line pair BL and BL, the potential changes of the bit line pair BL and BL caused only by the driving ability of the memory cell 12 are decreased from the bit line amplitude .DELTA.V to approximately .DELTA.V/2, respectively. As the result, attempts are made to speed up the time required to cause a potential change of bit line amplitude .DELTA.V between the bit line pair BL and BL on the basis of data stored in the memory cell to realize high-speed reading.
Conventional semiconductor storage devices which perform read operation of the ATD system such as SRAM are configured as described above, in which an equalizing operation of bit line pair BL and BL is made every time an address change is detected by the ATD control circuit 7.
In recent years, however, with developments of large capacity devices, the load capacitances of gates of transistors for access of memory cells connected to bit lines are increased to increase the equalizing time by the ATD system, resulting in a problem that the high-speed read processings are difficult.